Wafer-Level Encapsulation and Packaging of 3D Stacked Heterogeneous Microsystems

1)Low temperature process

Due to MEMS device is a multi-material integration system, in packaging step, process temperature must be well under control to avoid by-processes such as melting, crystallization, and stress creation. It is obvious that we have to look for low temperature process at which the MEMS device is packaged without any damage. The process also must be able to enable hermetic sealing. By understanding the technology advantages, we will focus on investigating soldering technology.

2)Wafer-level approach

As described above, to make the cost effective package, to increase the yield, and to protect the devices from the harsh environment especially during the dicing, the wafer level packaging is becoming the only solution. In line with the selection of low temperature process, we will investigate wafer level bonding by using the SLID (solid liquid inter-diffusion) technology. Process design and Optimizing the process parameter for WLP will be a major task. A practical process flow with optimized process parameter will be achieved to form WLP technology.

3)Defined hermeticity for 3D package

Hermetic packaging technology will consist with WLP. The technology we will work on must be met the requirement both for WLP and hermetic sealing. After achieving a proper solution for wafer level bonding, we have to work towards controlled vacuum package. The process parameters for hermetic sealing have to be determined.

4)Interconnection via sealing ring

Most of the MEMS devices need to provide the electricity from the outside of the package. The electrical connection might attack the sealing ring or the hermetic of sealed cavity if the fabrication of interconnections not fit for the fabrication of sealing ring. So the effect of interconnection fabrication based on optimized hermetic sealing ring will be discussed at the end of this project.